Complex
System Verification: The Challenge Ahead
Manufacturing capabilities are always outgoing the
capacity of current design tools. The advances in high level design brought
about by HDL languages as VHDL, Verilog, System C,
C++ etc. coupled with synthesis technologies has somehow addressed the complex
system design. Semiconductor fabrications can now put multi-million of logic
gates on a single chip using nanometer technology. Nowadays, the system
verification has become the main bottleneck in the development of complex
chips, systems on chip (SoC), multi chip modules
(MCM), printed circuit boards (PCB) etc.
With
switching speed well below 1ns in today’s gigahertz processors, and VLSI
circuit complexity exceeding the 100 millions
transistors per chip, power and signal distribution is characterized by
multi-gigahertz bandwidth pulses propagating through a tightly coupled 3D
packages and wiring interconnects. Signal and timing integrity (SI) and power
integrity (PI) are the most serious issues we need to address at 1GHz and
above. Timing is the single biggest factor affecting SI. About 15-20 years ago
components accounted for up 80% of the delay in a system. Today interconnect
alone accounts for the majority of the delay. Ability to identify and analyze
interconnect delays has emerged as a key differentiator in timely closure of
successful designs.
The MS-HDL
(VHDL-AMS, Verilog-AMS, System
C etc.) supports top-down design style and allows verification of large system
using mixed-level simulation. The combination of behavioral models; mixed
device, interconnect and macro models combined with low level circuit
simulations yield excellent results in many cases. Unfortunately, conventional
true-SPICE circuit verification tools fail to meet the timing and power closure
for multi-gigahertz non-linear circuits, high-speed interconnects and
electronic packages. We need a new generation of electrical modeling
methodology and sophisticated CAD tools which tie together high-speed
interconnects modeling, circuit simulation and computational electrodynamics in
one integrated design flow.
Next
generation of system verification tools must be able to do true
statistical/hybrid simulation of multi-gigahertz signals over microseconds of
time for non-linear mixed analog-digital circuits and systems with
·
multi-million
nodes and hundred-thousands transistors;
·
multi-million
extracted power/ground mesh RLC parasitics (huge
passive blocks);
·
simultaneous-switching
output simulations involving hundreds of inputs and outputs (I/O buffers), such
as those on a wide memory bus exiting a chip;
·
detailed,
fully coupled S-parameters modeling for the package and/or connectors with more
than 100+ ports;
·
ultrawide broadband analysis of
multi-gigahertz signals requiring extremely small picosecond
time-steps, over microseconds of time.
Advanced
interconnect modeling is a key to design modern complex mixed-signal circuits
and SoC. These models must be valid over a wide
bandwidth. The Scattering-parameters (S-parameter), in touchstone(R) files, may
be used to describe the frequency-dependent behavior of a complex interconnects
(traces, packages, vias, cables, interconnect
discontinuities etc.).
S-parameter
based macromodeling and S-parameter model generation
must be able to do:
·
real/complex
fitting to a frequency domain data;
·
passivity
enforcement;
·
poles
reduction;
·
control
model’s accuracy by reducing the order of rational polynomial approximation
(number of poles);
·
causality
check;
·
subcircuit generation;
and use the fitting results (poles)
directly in timing analysis.